Non-volatile electrically alterable semiconductor memory devices are well-known in the art. See, for example, U.S Pat. No. 4,203,158. In such a device, electrical alterability is achieved by Fowler-Nordheim tunneling of charges between a floating gate and the silicon substrate through a very thin dielectric. Typically, the thin dielectric is an oxide layer with a thickness of less than 100 angstroms. However, such a device requires a floating gate transistor and a separate select transistor for each storage site. Thus, necessarily, each storage site or cell is large due to the number of transistors required for each cell. Further, another disadvantage is the reliability and manufacturability problem associated with the thin oxide tunnel element between the substrate and the floating gate.
U.S. Pat. Nos. 4,274,012 and 4,599,706 seek to overcome the program of reliability and manufacturability of the thin oxide tunnel element by storing charges on a floating gate through the mechanism of Fowler-Nordheim tunneling of charges between the floating gate and other polysilicon gates. The tunneling of charges would be through a relatively thick inter-polyoxide. Tunneling through thick oxide (thicker than the oxide layer disclosed in U.S. Pat. No. 4,203,158) is made possible by the locally enhanced field from the asperities on the surface of the polycrystalline silicon floating gate. Since the tunnel oxide is much thicker than that of the tunnel oxide between the floating gate and the substrate, the oxide layer is allegedly more reliable and manufacturable. However, this type of device normally requires three layers of polysilicon gates which makes manufacturing difficult. In addition, voltage during programming is quite high due to charge trapping inside the tunnel oxide. Furthermore, the polysilicon to polysilicon tunneling voltage has a very wide statistical variation from cell to cell, wafer to wafer, and lot to lot. All these lead to a poor manufacturing yield.
Electrically programmable devices which are alterable by application of ultraviolet light treatment, typically known as EPROM devices, are well-known in the art. However, erasure requires erasure of the entire memory device by application of UV light.
Hot electron injection has been proposed by Dill and Tomes in 1969 on an MNOS structure (Vol. 12, Solid State Electronics) to improve switching speed and to reduce the need for a separate select transistor for each cell in a memory array.
Recently, U.S. Pat. No. 4,698,787 discloses a device that is programmable as if it were an EPROM and erasable like an EEPROM. Although such a device requires the use of only a single transistor for each cell, it is believed that it suffers from the requirement of high programming current which makes it difficult to utilize on-chip high voltage generation for programming and erasing. Further, it is believed that such a device requires tight distribution program/erase thresholds during device operation, which results in low manufacturability yield.